FPGA Verification Engineer

Job responsibilities:

    1. Write test incentive to conduct system function simulation and verification;
    2. Responsible for FPGA debugging;

Job requirements:

    1. Computer, electronic communication and related major, master’s degree is preferred;
    2. Familiar with Verilog language, FPGA development common software and process;
    3. Have a good digital circuit foundation, good English reading ability;
    4. Have good logical thinking ability and quick learning ability;
    5. Have team spirit and sense of responsibility;

Benefits:

    1. The salary is open, the outstanding person can interview;
    2. Project incentive;
    3. Equity incentive;
    4. Social security: pay five social insurance and one housing fund according to national regulations;
    5. Paid leave;

Post resume:

    1. Please send your resume to ychen@divimath.com.
    2. The resume is delivered as an attachment;
    3. Email and attached title: “name – major – education – school – job application”